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PRELIMINARY
CY7C1069DV33
16-Mbit (2M x 8) Static RAM
Features
* High speed -- tAA = 10 ns * Low active power -- ICC = 125 mA @ 10 ns * Low CMOS standby power -- ISB2 = 25 mA * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1 and CE2 features * Available in Pb-free 54-pin TSOP II package and 48-ball VFBGA packages
Functional Description
The CY7C1069DV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Reading from the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball very fine-pitch ball grid array (VFBGA) package.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
TSOP II Top View NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
2M x 8 ARRAY
I/O0-I/O7
COLUMN DECODER
WE CE2 OE CE1
A 10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 A19 A20
NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS NC A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC
ROW DECODER
SENSE AMPS
VCC
NC
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 125 25 Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05478 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 14, 2006
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PRELIMINARY
Pin Configurations[1]
48-ball VFBGA 1 NC NC I/O 0 2 OE NC NC (Top View) 4 3 A0 A3 A5 A1 A4 A6 A 7 5 A2 CE1 NC 6 CE2 NC I/O 4 A B C D E F G H
CY7C1069DV33
VSS I/O1 A17 V CC I/O 2 I/O 3 NC A19 NC NC A8 A18 A14 A 12 A9
I/O5 V CC VSS I/O 7 NC A20
A16 I/O 6 A15 A13 A10 NC WE A11
Note: 1. NC pins are not connected on the die
Document #: 38-05478 Rev. *C
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[2] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V DC Input Voltage[2] .................................-0.5V to VCC + 0.5V Range Industrial
CY7C1069DV33
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Ambient Temperature -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics Over the Operating Range
-10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND < VI < VCC GND < VOUT < VCC, Output Disabled Input Leakage Current Output Leakage Current Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 125 30 25 Max. Unit V V V V A A mA mA mA
VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels Automatic CE Power-down CE2 < VIL, Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs CE2 < 0.3V, Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
Capacitance[3]
Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V TSOP II 6 8 VFBGA 8 10 Unit pF pF
Thermal Resistance[3]
Parameter Description JA JC Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board All-Packages TBD TBD Unit C/W C/W
AC Test Loads and Waveforms[4]
50 OUTPUT Z0 = 50 (a)
All input pulses 3.0V GND Rise time > 1V/ns (c) 90% 10% 90% 10% Fall time: > 1V/ns
VTH = 1.5V 30 pF* *Capacitive Load consists of all
components of the test environment
3.3V OUTPUT 5 pF*
R1 317
R2 351 *Including jig and scope
(b)
Notes: 2. VIL (min.) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100s (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
Document #: 38-05478 Rev. *C
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PRELIMINARY
AC Switching Characteristics Over the Operating Range
Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE1 LOW/CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[7] High-Z[7] 10 7 7 0 0 7 5.5 0 3 VCC(typical) to the First Access[6] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW/CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z
[7] [7] [5]
CY7C1069DV33
-10
Description
Min. 100 10
Max.
Unit s ns
10 3 10 5 1 5 3 5 0 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High-Z
CE1 LOW/CE2 HIGH to Low-Z[7] CE1 HIGH/CE2 LOW to High-Z[7] CE1 LOW/CE2 HIGH to CE1 HIGH/CE2 LOW to Power-up[8] Power-down[8]
5
ns
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05478 Rev. *C
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PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[3] tR[11] Description VCC for Data Retention Data Retention Current VCC = 2V , CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 2
CY7C1069DV33
Typ. Max. 25 Unit V mA
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 3V tCDR CE VDR > 2V 3V tR
Switching Waveforms
Read Cycle No. 1[12,13]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2(OE Controlled)[13,14]
ADDRESS tRC CE1
CE2 tASCE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZSCE tPU 50% DATA VALID tPD 50% ISB ICC tHZOE tHZSCE HIGH IMPEDANCE
Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s 12. Device is continuously selected. CE1 = VIL, CE2 = VIH. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05478 Rev. *C
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PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1(CE1 Controlled)[15,16,17]
tWC ADDRESS
CY7C1069DV33
CE
tSA
tSCE
tAW tPWE WE tBW tSD DATAI/O tHD
tHA
Write Cycle No.2(WE Controlled, OE LOW)[15,16,17] OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tHZWE DATA I/O tLZWE tSD tHD
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0-I/O7 High-Z High-Z Data Out Data In High-Z Power-down Power-down Read All Bits Write All Bits Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE1 goes HIGH/CE2 LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. CE above is defined as a combination of CE1 and CE2. It is active low.
Document #: 38-05478 Rev. *C
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PRELIMINARY
Ordering Information
Speed (ns) 10 Ordering Code CY7C1069DV33-10ZXI Package Diagram Package Type
CY7C1069DV33
Operating Range Industrial
51-85160 54-pin TSOP II (Pb-Free)
CY7C1069DV33-10BVXI 51-85178 48-ball Very Fine Pitch Ball Grid Array (8 x 9.5 x 1 mm) (Pb-Free)
Package Diagrams
54-pin TSOP Type II (51-85160)
51-85160-**
Document #: 38-05478 Rev. *C
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PRELIMINARY
Package Diagrams
CY7C1069DV33
48-ball FBGA (8 x 9.5 x 1 mm) (51-85178)
BOTTOM VIEW TOP VIEW O0.05 M A1 CORNER 12 3 4 5 6 C A1 CORNER
O0.25 M C A B O0.300.05(48X) 6 54 3 2 1
A B C E F G H
5.25
A B
9.500.10 0.75
9.500.10
C D E
2.625
D
F G H
A B 8.000.10
A
1.875 0.75 3.75
0.55 MAX.
0.25 C
0.210.05
B
0.10 C
8.000.10
0.15(4X)
SEATING PLANE
0.26 MAX.
51-85178. **
C
1.00 MAX
Document #: 38-05478 Rev. *C
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY7C1069DV33 16-Mbit (2M x 8) Static RAM Document Number: 38-05478 REV. ** *A *B ECN NO. 201560 233748 469420 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF NXR
CY7C1069DV33
Description of Change Advance Data sheet for C9 IPP 1.AC, DC parameters are modified as per EROS (Spec # 01-2165) 2.Pb-free Offering in the `Ordering Information Converted from Advance Information to Preliminary Removed -8 and -12 speed bins from product offering Removed Commercial Operating Range Changed 2G ball of FBGA and pin #40 of TSOPII from DNU to NC Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page #3 Changed ICC(Max) from 220 mA to 100 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot spec in footnote # 1 Added Data Retention Characteristics table on page #5 Updated the 48-pin FBGA package Updated the ordering Information table. Added note# 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Updated the 48-ball FBGA Package
*C
499604
See ECN
NXR
Document #: 38-05478 Rev. *C
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